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Altera_Forum's avatar
Altera_Forum
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11 years ago

Serial communication and interval timer integration problems

I'm required to build a Nios based fpga firmware for a specific system, which includes UART RS-232 communication. The communication itself based on packets of 20 bytes, with time outs between bytes r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

When I use those functions for a creation a PWM signal, it works fine. Here is a real example:

I've created a PWM signal with a frequency of 10KHz, duty cyle is 1%. Period of 10KHz is 100us, DC of 1% means that output '1' should be for a 1us. With CPU clock of 50MHz, that means that the timer has to count 50 cycles, for a time out, and than process the ISR. It works, maybe I get the real DC of 1.5%, but this accuracy is fine for me.

Those hardware control functions, that I've written, they're just 1-10 lines of IORD/IOWR commands. How many CPU cycles those commands require?