Sequential Logic in Altera

I recommend you create a Verilog (.v file) or VHDL (.vhd) file in Quartus, then go to the edit menu and select "insert template". This will give you a bunch of different HDL (Hardware descriptive language) structured examples (including registers).

I also remember a HDL editor out there coming with a pretty good tutorial program for both VHDL and Verilog (these are the two main HDL language by the way)..... I forget what the name was but the editor did HDL entry and functional similuations. Maybe someone out there knows which one I'm talking about and can give jonb and mohana the name of it or some other good tutorial (google searching will find thousands of tutorials btw).