Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDRAM verify failed in NIOS II IDE
I work under QII5.0. My SDRAM is Micron MT48LC2M32B2-7. I choose the "single Micron MT48LC2M32B2-7 chip" in the "presets" of sdram controller setup menu. My SDRAM base address is 0x00800000. Whe...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by albs@Jul 1 2005, 12:49 PM the nios core and sdram peripheral operates (samples) on rising clock edges. sdram clocks out data on rising edges (valid on falling edges). if you do not run the sdram clock through a pll to tweak phase shifting, it will not work. if your sdram is very close to the fpga, you can get away with using an inverter (180 degrees). i have done that up to 96 mhz. if you have more than 2cm of distance between the sdram and fpga, you will have to use the pll and tweak the clock using an oscilloscope. have you tried using the fs2 console to modify sdram contents? --- Quote End --- http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif thank you so much!!Indeed the pll is necessary when you add a sdram to your system~
