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Honored Contributor
Honored Contributorsdram transfer
We have tested block transfer in sdram with memcpy() fonction on développement kit stratix 1S10 NIOS II with uclinux v1.1. The frequency CPU is 50Mhz. We obtained with nois ii /s (no data cac...
Altera_ForumHonored Contributor
Honored Contributorthanks for your help and your results
Ken, I agree with you. With a 75 Mhz 32b SDRAM you must obtain 300MB/s in burst (read or write). But when you chain single read and write transaction in different sdram page, you lost clock cycle. To increase performance, chain busrt read and burst write is better. I don't know if DMA can work in this mode. I don't think, because the DMA fifo depth is small.
