SDRAM signals managing

--- Quote Start ---

OK, what I have to do is to look at 4 signals (connected as the board GPIOs), store them somewhere then analyse it to tell what happens.

--- Quote End ---

Ok.

--- Quote Start ---

What I wanted to do is to store it in the internal FPGA RAM (it's easy) but lately it appeared the memory was to small and I decided to use the board SDRAM instead. But the mechanism of the SDRAM is too complicated for me so maybe I'll use a serial connection trough the USB to store it on the PC and analyse it with a simple software instead of an embedded one.

I'm listening for your advices in the matter...

--- Quote End ---

So, this is where "thinking" in terms of SDRAM has misled you. If instead you were thinking of Avalon-MM masters and slaves, then you need "something to read the GPIO" and "something to save the value read". There's numerous ways to do this, let me suggest a couple of options ...

1. Custom Avalon-MM master.

If the rate at which the GPIO pins are written is critical, eg., the rate has to be exactly 100Hz. Then you can create an Avalon-MM master that includes a 100Hz timer. When the timer expires, a control state machine can read the GPIOs, and then issue a write to an Avalon-MM master interface. You Qsys system can then connect that master to either internal SRAM or external SDRAM.

2. Standard Avalon-MM components.

A PIO input component can be used to provide read access to inputs. A DMA controller can be used to read the PIO and write to somewhere else, eg., SRAM or SDRAM. I haven't used the Altera DMA controller, but if it has a timer facility, then you might be able to setup a scheduled DMA transfer. Alternatively, you can use a NIOS II processor to perform the read of the PIO and write to SRAM/SDRAM.

3. Minimum effort.

Create a Qsys system with a GPIO port and a JTAG-to-Avalon-MM bridge and read the GPIO from your PC. The SDRAM example I provided you already has the JTAG interface, so all you need to do is add a PIO component and connect it to your GPIO pins.

If the rate at which the GPIO is read is not critical, then (2) or (3) would be a good place for you to start.

Cheers,

Dave