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Altera_Forum
Honored Contributor
Honored ContributorSDRAM signals managing
Hi, I'm using qsys to implement a system on Quartus II. I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's anot...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- That was only for test. Forget it. --- Quote End --- Huh? Why would you forget it. As a design engineer your task should be to "design" the stuff that is unique to your project, and not re-invent the wheel when a perfectly good wheel exists. So, if your project needs to use an SDRAM controller, and you need to write some custom logic to access the SDRAM in parallel with other "standard" components like a NIOS II processor, then your custom logic needs to "play nicely" with the rest of the system. Basically this means that your custom hardware has to fit within the Avalon-MM architecture used by the other components in your system. What does your custom logic have to do? Lets figure out whether you need to create an Avalon-MM master, or an Avalon-MM slave that interfaces to a DMA controller. Cheers, Dave
