Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

SDRAM signals managing

Hi, I'm using qsys to implement a system on Quartus II. I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's anot...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I have three new questions:

1-How to make the SDRAM available both for the software part (a Nios II cpu in a Qsys system) and the hardware part (a Quartus II design)?

2-How to tell Qsys that the program of the cpu should be stored in the internal FPGA memory and the data should be stored in the SDRAM?

3-I've downloaded this file: http://www.altera.com/products/ip/altera/ocore_sdr_sdram.html

and a first problem is the address bus width. In the file it's 12-bit but in the first qsys system it was 13-bit.

Thanks.