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Altera_Forum
Honored Contributor
Honored ContributorSDRAM signals managing
Hi, I'm using qsys to implement a system on Quartus II. I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's anot...
Altera_ForumHonored Contributor
Honored ContributorPlease take a look at the DE0-nano SDRAM example in this thread:
http://www.alteraforum.com/forum/showthread.php?t=45927 That will give you a working design, including SDRAM timing constraints (see the .SDC file), which for some reason the IP does not include. Cheers, Dave
