Dear Friends, i am trying to write and read data in SDRAM. but while writing and reading i don't have any control over address where i perform my read/write operation. i am using following commands for read and write operation. IOWR_ALTERA_AVALON_PIO_DATA((SDRAM_BASE),my_data) and for reading i am using IORD_ALTERA_AVALON_PIO_DATA((SDRAM_BASE) every time i run my code it start writing SDRAM from first location and while i read SDRAM it will return (again and again ) value which i write at the place where i stop writing the SDRAM. like if i write 1,2,3,4,5,6,7,8,9 and the if i read it return 9,9,9,9,9,9,9, again and again...it seems like my SDRAM read address stuch at the last address. kaushal

This is expected, since you are always writing to the same address. The macro you use is for a PIO. To read/write any location, you can use: IOWR(SDRAM_BASE+address,my_data) IORD(SDRAM_BASE+address) Use address=0 to write at the first location, and remember that it is a byte based address, i.e. use address=4 to access the second 32-bit location, 8 for the third one, etc...

If you compile your code into that same SDRAM be careful with cache coherency. For example if you malloc some memory and use cache bypassing macros to access it you might find old data will get moved to the SDRAM instead of what you intended. The reason why is if you access memory using IOWR that happened to be cached previously the CPU hardware will write out the cache line instead of the data from IOWR (really there is no right answer as to which one should win so just avoid this case). You can avoid this by flushing the cache before performing the IOWR accesses or write your code using cache bypassed pointers using the HAL cache remapping functions which will do the flushing for you.

Thanks now i am able to read write in SDRAM with desire address.

I try to test SDRAM chip. Kindly advice me when the example driver method is use to test the SDRAM and when the read and write functions (IORD & IOWR) are used to perform the same test

I try to test SDRAM chip. Kindly advice me when the example driver method is use to test the SDRAM and when the read and write functions (IORD & IOWR) are used to the same test

SDRAM Read and write address control | Altera Community

15 Replies

Altera_Forum
Honored Contributor
15 years ago
@daixiwen

now i can read and write at the desired offset.
thanks a lot daixiwen
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
@ badomen

how do i flush the cache??

i keep getting the wrong value... example: i wrote the offset 0 with 0x23, and then i read this offset and i get the 0x23. but then i wrote the offset 3 with 0x14 and then i read in offset 0 and i get 0x14. isn't it supposed to be 0x23??
--- Quote End ---

I would attach your code to a post since any number of things could be happening. The only time I would expect the issue you are seeing is:

a) When you say offset 3, if you are talking byte offset 3 and performing a 16/32 bit access then that is not allowed (unaligned access)

b) You are mixing cached and non-cached accesses to the same memory location

If you are doing neither then bypassing the cache shouldn't solve this problem and it's most likely something else causing the issue.
Altera_Forum
Honored Contributor
15 years ago
.... oops I should read more, looks like you are up and running.
Altera_Forum
Honored Contributor
15 years ago
@badomen

yeah ^__^
anyway thanks for replying... apparently i used the wrong macros
Altera_Forum
Honored Contributor
15 years ago
Ok just make sure to avoid# 2 from my other post. It's a common mistake that I've done myself. Typically it happens when you attempt to bypass the cache to write data to main memory using IOWR. If you also use the same memory for code (in particular stack/heap) that memory might have been previously used and cached which combined with IOWR will cause a cache coherency issue.

Forum Discussion

SDRAM Read and write address control

15 Replies

Recent Discussions

licensing.altera.com never worked

NiosV and juart-terminal

NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)

JTAG_UART stuck in printf

Ashling IDE scripted project creation