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Altera_Forum's avatar
Altera_Forum
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16 years ago

SDRAM Read and write address control

Dear Friends, i am trying to write and read data in SDRAM. but while writing and reading i don't have any control over address where i perform my read/write operation. i am using following ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

If you compile your code into that same SDRAM be careful with cache coherency. For example if you malloc some memory and use cache bypassing macros to access it you might find old data will get moved to the SDRAM instead of what you intended. The reason why is if you access memory using IOWR that happened to be cached previously the CPU hardware will write out the cache line instead of the data from IOWR (really there is no right answer as to which one should win so just avoid this case).

You can avoid this by flushing the cache before performing the IOWR accesses or write your code using cache bypassed pointers using the HAL cache remapping functions which will do the flushing for you.