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Altera_Forum
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20 years ago

SDRAM PLL clock output

Has anyone ever got the following warning regarding the SDRAM PLL clock output: warning: pll "sys_pll1:sys_pll|altpll:altpll_component|pll" output port clk[2] feeds output pin "sdram_clk" via n...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

You should check the pll chapter on the device handbook.

The input clk and output clk must feed to/from the same pll directly.

If the input clock does not match the pll, it wont fit.

If the output clock does not match, it will warn of the jitter.