SDRAM does not retain data

Marco,

just want to emphasize Clancy's point regarding the SDRAM clock phase. This phase seems to be very critical (at least at higher CPU clocks), and it depends on place & route.

In my specific design I had to ...

1) lock down the SDRAM-controller to a logic lock region close to SDRAM IO pins in order to freeze timing

2) adjust PLL parameters manually in the chip editor to values I was not able to get using the wizard.

Failing to do so resulted in arbitrary error patterns ranging from steady failure up to passing memory tests with data read/write but sporadic failures during code execution.

Rolf