SDRAM core parameters

Hi all

In my board i use SDRAM k4s561632E-tc75 -

it have 256Mbit size

Datawidth 16

Banks -4

Row 13

Col 9

I use 2 chips so 2 Chip selects

I have verilog behaviour model of it

And it has next timing parameters

`define tCCmin 7.5 // clock minimum cycle time

`define tCCmax 1000 // clock maximun cycle time

`define tCC3 7.5 // clock minimun cycle time at cas latency=3

`define tCC2 10 // clock minimun cycle time at cas latency=2

`define tCH 2.5 // clock high pulse width

`define tCL 2.5 // clock low pulse width

`define tSS 1.5 // input setup time

`define tSH 0.8 // input hold time

`define tRRD 15 // row to row delay(min)

`define tRCD 20 // ras to cas delay(min)

`define tRP 20 // row precharge time(min)

`define tRASmin 45 // row active minimum time

`define tRASmax 100000 // row active maximum time

`define tRC 65 // row cycle time(min)

`define tCCD 7.5 // col. address to col. address delay:

`define tSAC2 6

`define tSAC3 5.4

`define tSHZ2 6

`define tSHZ3 5.4

And i can't find correspondence with SOPC SDRAM parameters

i'm know how SDRAM works in idea only and i don't know how exactly it working

so can someone help me to find correspondence with next parameters, please

Cas latency cycles 3 (it's looks correct )

Initialization refresh cycles 7 (i assign big value but may be i'ts incorrect)

Issue one refresh commant every 7.8125 (i set it like 64ms/8192 cyles so it looks correct )

Delay after powerup,before initialization 100 us (not changes )

Duration of refresh command (t_rfc) 80 (don't know )

Duration of precharge command (t_rp) 20 (don't know )

ACTIVE to READ or WRITE delay (t_rcd) 20 (don't know )

Access time (t_ac) 6 (don't know )

Write recovery time (t_wr, NoautoPrecharge) 20 (i don't know)

Can someone correct my parameters or tell how and where get it , because i saw datasheets

and i did't saw that paramereres in clear form.