running sw in SDRAM

Indeed, indeed, The PLL tuning.

The delay was on -4ns.

In a small test project, it turned out that -3ns untill +1ns works for both instruction fetching and data access.

Mean time I found the document sdram controller (http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf) and used the calculations to estimate the timing, it turns that the shift should be -2ns average.

I decided to use -1.5ns, and the SDRAM works fine also in the real project.

Thanks for the hint.

Stefaan