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Altera_Forum
Honored Contributor
Honored Contributorrunning sw in SDRAM
Hello, I want to use SDRAM for a small set of functions, toghether with big chunks of data. The rest of the software runs from SRAM. I verfied the correct working of the SDRAM, the instruc...
Altera_ForumHonored Contributor
Honored ContributorIndeed, indeed, The PLL tuning.
The delay was on -4ns. In a small test project, it turned out that -3ns untill +1ns works for both instruction fetching and data access. Mean time I found the document sdram controller (http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf) and used the calculations to estimate the timing, it turns that the shift should be -2ns average. I decided to use -1.5ns, and the SDRAM works fine also in the real project. Thanks for the hint. Stefaan
