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Honored Contributor
Honored ContributorRunning SDRAM at double speed
I currently have a NIOS1 design (but I think this will apply to NIOS2 as well) running at 60MHz, with 16 MB SDRAM. The internal SOPC clock is PLL-ed to 60MHz and the E0 output (also 60 MHZ) is ...
Altera_ForumHonored Contributor
Honored ContributorIn my tests with my custom Cyclone board, I found that I could run out of onchip ram to 140MHz, run out of onchip but use SDRAM for data to 120MHz. I could use SDRAM for instruction and data to 112MHz.
On my board, I required only one PLL (CPU and SDRAM share) with no delay. I placed the 16MB SDRAM module close to the Cyclone and routed every signal on the top layer. Ken
