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Altera_Forum
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14 years ago

running program in SRAM doesn't work

Hi all, I am running my C program in NiosII and I need to print out the result on the console. There are a 512KB SRAM and an 8MB SDRAM on the board. The program works fine with the SDRAM. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I feel like a *****, but i tried to make my own tri-state version as suggested by BadOmen; but this failed. I require more help and would be greatly appreciative.

It failed the same as before with the .elf failing verification upon download. Likely because i have no idea how to set up the Tri-state controller, i did alot of googling and read some doco and made an attempt anyway.

I have attached a zip file with screenshots of my attempt. In summary but my problems were:

  1. signals?:Couldn't match my SRAM's signals to those avaliable in the Tristate controller. My SRAM has no read enable, it also has two other signals, upper and lower?

    I took a guess that these two mystery signals could be bridged to WE since they appear optional and a timing diagram where they were used they matched WE.

  2. parameters had me stumped. I used the preset on the right for the IDT SRAM as a starter.

    Two worse ones was that driver one since it made no sense what the preset put there. Plus i put the bytes value there, but am i meant to take some off? As in 2MB seems too round?

  3. timings: I couldn't match the timings. In many cases i made an educated guess or put a worse case value.

what i tried summary

  1. Made simple Qsys design of nios. Onchip ram contains Nios vectors.

  2. Made tri-state control and connected to a tri-state bridge. note i doubt the control is correct.

  3. Made top level and bridge the 3 signal WE,UB, LB.

  4. Made simple "Hello World Nios" and pointed its memory to the SRAM controller.

attached

  1. Data sheet. Note that its the 8ns model.

  2. QSys image.

  3. Tri-state control set up images.

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Dear AsValdr,

Do you noticed that in your Qsys GUI, the address arrange of sram is 0~0xfffff, it's just 1M byte. But in fact the memory size of IS61WV102416 is 1M x 16 bit, it's 2M byte. In Generic Tri-State Controller, the Address width is the byte width, not the actual address width of SRAM, and 2^20 = 1M.

Thus, if I fill 21 here, the address arrange will expand to 2M, but one more address line come out, MSB or MLB? how to instantiate it in verilog?