Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

rubbish out of uart in multiprocessor design

I've got a design with two nios2 cpus which have a uart component and the jtag uart on cpu1. At present I'm just sending some data from cpu2 to cpu1 via shared memory and a mutex. When cpu1 g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

I fixed the problem. In SOPC Builder I set up the baud rate for the uart component as 9600 baud. I had a second PC connected to the uart in order to monitor the garbage from the uart. Bizarrely, upon configuring the program in the monitor PC to run at 4800 baud, the output from the uart became sensible! Presumably this means that the uart's divisor register is being set wrongly; perhaps in SOPC Builder?