Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi,
--- Quote Start --- Of course this does not work that easy with multiple CPUs. but here a hardware flag that is set before and reset after the would be atomic instruction by a custom instruction (that other than an I/O access can be executed in user space) could be used to do a spinlock and the interrupt issue might be handled in a similar way as with a single CPU system. --- Quote End --- I know your idea, but where do you make the hardware flag? The NIOS CPU has 6 pipeline stages Fetch, Decode, Execute, Memory, Align and Write back. Maybe the custom instruction's hardware belongs to the 'Execute' stage, but we don't know which stage accepts the interruptions. So maybe, we can't solve the delicate timing problem between the flag set/reset and interruptions. Moreover, after applying the CONFIG_PREEMPT_RT patch, it is quite natural that someone will ask 'Does anyone build the kernel with CONFIG_SMP?' . So I think it's better for us to keep the original aspect of kernel sources and put the ungraceful parts into the machine dependent 'MACRO'. Now I'm seeking another way. Kazu