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Altera_Forum
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13 years ago

ROM using altsyncram: timing question

Hi, Another newbie question. I have a simple ROM attached to my CPU, courtesy of altsyncram, and initialised using a .HEX file. All works, both in simulator and in the chip. My VHDL d...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The altsyncram component has input and output registers. This means that when you assert an address, the output data (q) does not update for two clocks.

Cheers,

Dave