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the NIOS reset appears to be sourced via the JTAG debug module ...
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Appears? It likely has an option to reset via JTAG. However, in a deployed system, that is not going to be the only way to reset the processor.
If you have not created a simulation of a NIOS II processor, then I'd recommend creating a simple design with one. Creating a simulation where you can hold the processor in reset, deassert reset and allow it to boot, and then repeat that sequence, will go a long way in helping you understand how to do it in hardware.
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I believe you indicate I need to control the NIOS reset explicitly , ie disonnect it from the JTAG debug reset and generate a reset to the system that starts once the FLGA is configured and receives the first functional clock. ?
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Reset is "just a signal". The clocks on a board can power up, and other logic can come out of reset, eg., a PCIe endpoint can come out of reset, that end-point can be used to manipulate bits, and one of those bits can be the NIOS II processor reset signal. This provides a mechanism where you can download to the NIOS II processor boot memory over PCIe, then release it from reset, and it will boot.
Cheers,
Dave
Honored Contributor
