"Rescue" monitor idea

I've just done this. But one caveat - my NIOS code is embedded in the FPGA image in an M4K onchip memory - I'm not loading NIOS code via the EPCS boot loader.

I have room for two FPGA images in EPCS. At POR, FPGA image 0 is loaded. My software then:

- checks whether or not FPGA image 1 is present in the EPCS

- reads the remote upgrade core to make sure that we are running in FPGA image 0

- reads the remote upgrade core to make sure that we didn't load FPGA image 0 because of a watchdog or CRC failure in FPGA image 1,

- (optional) checks an external indication to see whether or not to load FPGA image 1,

- and if all systems are go, sets the reconfig address in the remote upgrade core, and triggers a reconfig.

When I upgrade, I will ALWAYS overwrite image 1, doing just sector erases for image 1.

AND - alas, Altera has NOT provided an avalon core for the remote upgrade megafunction - you have to add your own logic to connect it to your SOPC system. One hint - I found that you just need to assert read or write to the megafunction for 1 clock cycle. If you leave read or write asserted, you might find that your write works, but reads don't.

If you are using the EPCS boot loader, you will need to figure out how to tell the EPCS loader to use the FW that follows FPGA image 1 instead of FPGA image 0.

\chuck