Remote update IP CRC

Hi there,

During the read operation, the flash memory controller sends a command to the flash memory to fetch the desired data. However, due to the internal operation of the flash memory cells and the nature of serial communication, there can be a delay between sending the command and receiving the actual data. Sometimes, for cyclone device, some flash’s dummy clk cannot meet for the delay requirement for cyclone, quartus may insert some ”FF” as “fake dummy clk”. So these “FF” will not check by crc, because it will not read into cram. And in the rpd, there is a “header” which is not belong to logic part, the crc circuit is used to make sure your logic part work well.

For the last 576 bytes, it used for the jump mechanism of RSU, it also will checked by RSU circuit. However, if damage occurs, crc cannot guarantee 100% detection.

Best regards,

WZ