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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

"readyfordata" won't work

Hi Guys, I'm trying to build an MM Slave component with dataflow control and got some problem. It is very important, that if the target is not ready to receive data then NIOS must stop writing ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have found the solution for this issue. You guys told really the keyword. So the point uis that the master must support flow control, and yes, the cpu itself does not support that (except the waitrequest, what is really also a signal for FC, never mind...). The solution is to insert some Master/Slave component what supports the FC on the master side, and does not need FC on the slave side, for example DMA. I have done this, and now it works perfectly. "readyfordata" is not ignored now.

So, you guys were helpful again, thank you!