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Altera_Forum
Honored Contributor
Honored Contributor"readyfordata" won't work
Hi Guys, I'm trying to build an MM Slave component with dataflow control and got some problem. It is very important, that if the target is not ready to receive data then NIOS must stop writing ...
Altera_ForumHonored Contributor
Honored ContributorYou didn't understand rbugalho's answer. This feature isn't deprecated or not supported anymore, it is optional. It will only work if both the master and the slave support it. The Nios CPU doesn't support it, so you won't have flow control as long as you use the Nios CPU to access your peripheral.
Furthermore, use of flow control on the MM interface would freeze the CPU until the slave is ready to receive data, which may not be what you want. You can use a DMA engine such as the SGDMA to transfer data between memory and a component on an ST interface. This is the recommended way when you need flow control, and the CPU can do something else while the slave is stopping the flow.
