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Altera_Forum
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13 years ago

Reading Interval Timer Core snapshot from an ISR

Reading Interval Timer Core snapshot from an ISR Hi all i have a strange problem regarding reading Interval Timer Core snapshot from an ISR. IRQ is triggered by custom UART interface pe...
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Altera_Forum
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13 years ago

We implememented a simple 32bit avalon slave with 1ms (for timers) and 100MHz (Nios cpu clock) non-resetable up-counters and used those for performance/timing measurements.

We also count some async events - remember to sync the event to the Avalon clock, attempts to sync the counter give unexpected values during (ripple) increments.