Honored ContributorIf you make a custom MM slave component, the standard template does not include readdatavalid or waitrequest. Does this mean that if the component does not need to insert wait states these signals can be left out of the component design?
Honored Contributoryes, you are correct.
Honored ContributorThe default is no wait states on writes (slave latches data on first rising clock edge), and one wait state for reads (slave drives data on first rising clock edge, master samples on the second).
Honored ContributorWaitrequest *is* required if the slave port does not have a fix read latency or may block write accesses. Even if it's variable latency your component can only accept a pre-determined number of read accesses and must assert waitrequest if it has not returned any of the data if another read is attempted.
Readdatavalid is only required if the slave port supports pipelined reads but does not have a fixed latency. As soon as you add a readdatavalid signal to your interface it *cannot* be fixed latency. Last but not least if your component supports variable read latency using the readdatavalid signal your slave port *must not* assert readdatavalid the same cycle that the read address phase completes. The read address phase is considered complete when read == 1 and waitrequest == 0.
