Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Read wait on nios component not working / bus timing problem ?

Hello, I have made a Nios/qsys VHDL component. The component has a read wait of 2 cycles (defined in signals & interfaces in qsys). (See attached JPG) In the component I implemented for ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Solved,

Value of 0xFF is correct.

Interpretation of timing diagram was the problem.

Best Regards,

Johi.