RC5.vhdl

Hi

Why you don't write this to whitebream and ask for help?

whitebream wrote for the RC5 VHDL Core on his page:

"The project that this core was designed for is cancelled before any hardware was available. Therefore this decoder has never been tested on real hardware. When you implement this core please provide feedback on any changes that are needed to get it working or just bugs and comments in general."

I downloaded this core and I'll view it's code for my own interesting in next days. If I found any hints I'll let you know this.

Greetings

Jens

Hi

The code of that core is quite short so I take a look before going to lunch http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

I assume that the instantiation is correct

If you leave the constant CLKS4BIT unchanged...

> -- Calculate the number of clock cycled in each RC5 bittime

> -- (which is 1.778ms)

> constant CLKS4BIT :integer := SYS_CLK / 562;

...the sampling rate will be 89kHz at 50.000.000Hz SYS_CLK. The accepted pulse width of incoming RC Bits is nearly 45us (about 22.000 Bits/s). A very high transfer value for a simple IR diode.

What is the result of the simulation? What is the used source of RC pin?

Hope, this give you a hint

Greetings

Jens

Hi Jens

Thanks for the help.

I use remote control that work with RC5 protocol.

The IR chip works on 38KHz.

I run a simulation and I got that the reg_full is going high &#39;1&#39; and the state machine is getting to finish state, but the interrupt is NOT going down to &#39;0&#39;

I am changing the code to fix it.

Tal

---------------------------------------------------------------------------------------------

I found the bug : they forgot to reset the reg_full on reset. (reg_full <= &#39;0&#39;;)

Now it&#39;s work fine.

Thanks

Tal

--- Quote Start ---

Hi Jens

Thanks for the help.

I use remote control that work with RC5 protocol.

The IR chip works on 38KHz.

I run a simulation and I got that the reg_full is going high '1' and the state machine is getting to finish state, but the interrupt is NOT going down to '0'

I am changing the code to fix it.

Tal

---------------------------------------------------------------------------------------------

I found the bug : they forgot to reset the reg_full on reset. (reg_full <= '0';)

Now it's work fine.

Thanks

Tal

--- Quote End ---

hi Tal_nios,

could you help me concern your rc5 code ?

thanks