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Altera_Forum
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19 years ago

RC5.vhdl

Hi, I have a RC5 module from the web site :www.whitebream.com I work with cyclone :EP1C3T100C7 , the clk is 50Mhz, I changed the CLK_SYS in the module to 50M, but the RC5 module is not respondin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi

The code of that core is quite short so I take a look before going to lunch http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

I assume that the instantiation is correct

If you leave the constant CLKS4BIT unchanged...

> -- Calculate the number of clock cycled in each RC5 bittime

> -- (which is 1.778ms)

> constant CLKS4BIT :integer := SYS_CLK / 562;

...the sampling rate will be 89kHz at 50.000.000Hz SYS_CLK. The accepted pulse width of incoming RC Bits is nearly 45us (about 22.000 Bits/s). A very high transfer value for a simple IR diode.

What is the result of the simulation? What is the used source of RC pin?

Hope, this give you a hint

Greetings

Jens