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Honored Contributor
Honored ContributorRandom Resets
I have a design built into a Cyclone III running uClinux on a NIOS II at 100 MHz. I am seeing random resets (linux reboot). They may be tied to accessing a pio in SOPC, but I do not have enough data ...
Altera_ForumHonored Contributor
Honored ContributorFirst thing to check with odd behavior like this is that you are meeting timing requirements on the FPGA build. In particular with the memory controller.
Jake
