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Altera_Forum's avatar
Altera_Forum
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16 years ago

Random Resets

I have a design built into a Cyclone III running uClinux on a NIOS II at 100 MHz. I am seeing random resets (linux reboot). They may be tied to accessing a pio in SOPC, but I do not have enough data ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

First thing to check with odd behavior like this is that you are meeting timing requirements on the FPGA build. In particular with the memory controller.

Jake