questions about flash in nios

Hi,

1. Yes, you can store any data application (software image) in the unused memory portion in the flash device. As long these data are not overlapping the configuration data. The data application (software image) can be store after the last byte of configuration data.

2. You can refer to the FPGA uncompressed .rbf size to know the space require to store the configuration data in flash device. Refer to the FPGA datasheet for the uncompressed .rbf size.

3. Unfortunately I'm not familiar with NIOS. Perhaps you can refer to the Nios flash programmer user guide to start off.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_nios2_flash_programmer.pdf

4. You can use Quartus II programmer to read and write data into the flash device.

thanks!

1. i think both the hardware image and the software image can not be changed, i think the configure data contains hardware image, software image and the bootloader. i want to know the size of the configure data( hardware image, software image and the bootloader) or where the configure data ends.

2. i can not find the rbf file, can your give me more details?

3. i do not want to W/R the flash in flash programmer, i want to W/R the flash in the main.c,

4. i do not want to W/R the flash in Quartus II programmer, i want to W/R the flash in vhdl.

i want to tread the unused flash space like a flash device that i can W/R in my code when the fpga is running, not just once.

You can get information about your configuration data addresses when you generate the .jic or .pof files with your hw and sw. It should be generated into an <output_name>.map file, which is simply a text file with the address ranges for you hw and sw.

You can write to flash from nios if you have the epcs_flash_controller module instantiated. You will need this module anyway b/c that is how you bootload the fpga from flash. (and this assume SPI flash).

I'm sure there are VHDL examples of r/w to flash.

thanks!

i use flash programmer to download the hardware image and software image, so there are no .jic and .pof file.

and i try to find the .map file, i still can not find it.

someone told me how to genrate the jic file, i try to do that, still failed:

thanks!

i try to generate the .jic file

when i use "sof2flash --epcs --input=ex2.sof --output=hw.flash --verbose" the command shell tell me "please supply an offset where you would like your sof located <--offset>"

so i use "sof2flash --epcs --input=ex2.sof --output=hw.flash --verbose --offset=0x0 "(i do not know whether offset=0 is right)

then the hw.flash file is generated

then i use "elf2flash --ecps --base=0x0 --end=0x7ffff" --after=hw.flash --input=test2.elf --output=sw.flash"(0x7ffff is the size of M25P40 )

then the sw.flash file is generated, but its size is 1Kb and content is

"S00600002D454C3B

S70500000000FA"

i do not think it is right, so i think the base and then end address may not refer to M25P40, so i change them to base and end of EPCS/EPCQx1 Serial Flash Controller in Qsys, that is 0x01001000 0x010017ff

then i use "elf2flash --ecps --base=0x01001000 --end=0x010017ff" --after=hw.flash --input=test2.elf --output=sw.flash"

then the command shell tell me

"elf2flash: Boot copier file name required

elf2flash: Error generating Flash file, exiting"

i do not know where to find the Boot copier file....

can you give me more advise?

thanks!

Try generating the flash files in NIOS flash programmer. Call it from NIOS IDE. You can uncheck program device, just generate the flash files. Then you can convert the sw.flash file into sw.hex in the nios command prompt.

Take a look at my thread: http://www.alteraforum.com/forum/showthread.php?t=48733

Hi qd0090,

For the FPGA .rbf size, just refer to the FPGA datasheet for the uncompressed .rbf size. I don't know which FPGA you want to use but here is an example Arria V .rbf size from the datasheet. Refer to Table 1-72: Uncompressed .rbf Sizes for Arria V Devices from the following link:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/arria-v/av_51002.pdf

my device is not max10.

i need a epcs to configure the fpga after power on.