Question about interfacing 8 bit Custom components to Nios II bus.

When Nios II was released the Avalon-MM specification stated that during reads all byte enables need to be asserted. Since Nios II is a 32-bit processor as a result a full 32-bit read would occur and it would filter out the bytelanes that were not necessary. Since then the spec was loosen to allow other supported byte enable combination on read cycles. Nios II was not updated to take advantage of this since it may break existing systems.

I recommend making your custom component interface 32-bits wide and just ground bits 31 downto 8 so that you don't consume extra resources. On write cycles qualify the writes by making sure write == 1 and byteenable[0] == 1. This will prevent the four byte reads from being chopped into four consecutive byte reads.