Honored Contributor
Honored ContributorOk, then this is correct you probably have run into the second issue I describbed. When I used +4 and +8 those are the word alignments on the Nios side, but the peripheral itself will be knocking off the two lsbs of the address. I have lost track in this long post what the peripheral is but I seem to recall it's some 8 bit native peripheral. Because it is an 8 bit device it byte offsets of 1, 2, and 3 all map to the same address on the peripheral side (you are just lining up the 8 lsbs of the data from the avalon bus to the 8 data bits of your peripheral so trying to write to bits 31..8 doesn't really make much sense). Here is an example that I hope clarifies this (well at least I attach a link to a document that explains this if my example doesn't do the job):
I have some piece of logic that I want to connect to the interface to user logic. My data width is 8 bits, and I have 6 registers to write to externally. The IUL will connect address bits 5..3 from the avalon bus to bits 2..0 on the external interface (where you connect your hardware). So I would access these registers in my software from offsets of 0, 4, 8, 12, 16, 20. But on my external interface I'll see addresses of 0, 1, 2, 3, 4, 5 (because the avalon addresses 5..3 were mapped to external addresses 2..0). So address bits going from the avalon bus to the external bus are simply being shifted to the right by two bits (the two lsbs are not used because they are not necessary with a 32 bit master writing to an 8 bit slave). This may seem odd but it serves a very important purpose when it comes to masters of different widths trying to use a peripheral like this. Using that example lets say another master of only 16 bits is used. In this case to properly align the address bits only the first lsb will be knocked off (so an address shift by 1 bit to the right). The IUL knowns to do the proper shifting depending on the data width of the master (so with the 32 bit master it'll access offsets of 4, 8, 12, etc... and the 16 bit master will access the peripheral at offsets of 2, 4, 6, etc...) But looking at the external addresses going to the peripheral, the offsets will be always 1, 2, 3, 4, etc..... (so your hardware pepripheral is transparent to the width of the master). I recommend taking a look at this document "Avalon Bus Specification", http://www.altera.com/literature/manual/mn..._avalon_bus.pdf (http://www.altera.com/literature/manual/mnl_avalon_bus.pdf) <page 100>. It has a table showing what I explained, only it probably makes more sense since describing hardware in plain text is tricky. Let me know if this is making sense or I have just steered you down the wrong path further.
