QUARTUS 4.2 NIOS 1.1 UPDATE PROBLEM

I'm not happy with the update to Quartus 4.2 and NIOS 1.1

I received the following answer from Altera for my problem with user logic,

but I do not understand this answer.

------------------------------------------------------------------------------

Problem:

"Why does my embedded system fail to compile after upgrading to Quartus II

version 4.2 due to an address width mismatch?"

Solution:

"In previous versions of Quartus II, SOPC Builder created an extra most

significant address bit for registered slave peripherals (also called

native peripherals) connected to an Avalon Tri-State Bridge. If this bridge

has only native slave devices connected to it then some designers may have

connected this extra address bit in their design to a peripheral. This extra

address bit no longer exists if the embedded system is regenerated using

Quartus II version 4.2. If a design is using the extra address bit and

the Quartus II software is upgraded to version 4.2 then a compilation error

will occur due to the most significant address bit not being connected.

This issue can be corrected without the need to modify software or

hardware interconnects. If the peripheral affected by this issue is connected

to an interface to user logic, then increasing the address width by one

(in the interface to user logic) will correct the issue.

If the peripheral affected by this issue is a custom component,

edit the "class.ptf" file for that component by increasing the value

called "Address_Width" by one."

------------------------------------------------------------------------------

1. the design could be regenerated and compiled with Quartus 4.2 without error

2. the bridge has additional ram and flash connected.

3. I entered 8 address bits in SOPC builder and I connected exactly 8 address

bits from the address bus to my user logic. (which extra address bit ???, how

can I see this in a shared address bus? )

again:

I have an 8 bit avalon register slave.

address bus is shared with SRAM AND FLASH

Address A[9..2] are connected to A[7..0] of 8 bit slave

Interface to user logic:

PORTNAME WIDTH DIRECTION SHARED TYPE

address 8 input yes address

write_n 1 input yes write_n

read_n 1 input yes read_n

data 8 inout yes data

chipselect_n 1 input --- chipselect_n

irq_n 1 output --- irq_n

IORD and IOWR do not output the cortrect address on the bus.

is this a bug in SOPC Buider 4.2 ?

Quartus 4.2 ?

NIOS 1.1 ?

is it only a project conversion problem from 4.1 to 4.2 ?

(I regenerated the system in SOPC Builder 4.2 and recompiled with Quartus 4.2)