Qsys MM modules used a standalone IP cores?

The UART is generated in plain text, so you can take it and modify it however you like. The Avalon-MM Slave is quite contained, and looks easy to remove/bypass should you care to.

Alternatively, it is not very difficult to add an Avalon-MM Master port to your standalone VHDL and have it master the UART that way. You might prefer this arrangement in order to avoid having to take ownership of the maintenance of the UART module (but I think that is low risk, since the module is quite simple to start with and hasn't changed recently).