Altera_Forum
Honored Contributor
9 years agoQsys Address Mapping Query
I have a Qsys design in which NIOS II data master is connected to Avalon slave of peripheral (Stepper driver). Here the width of the address bus of the peripheral is 3-bits. So, when I assign base address for the peripheral, I was expecting the tool to assign the end address automatically by looking at the address bus width of the peripheral. Hence, if I assign base address as 0x0000 0000, i was expecting to see the end address as 0x0000 0007 (because the address bus is 3-bits). But the tool assigned the end address as 0x0000 001F. When I checked the HDL of Qsys design, I understand additional 2-bits has been appended to the address bus. I am totally confused on this. I know I am missing out something. Can anybody enlighten me on this?