Forum Discussion
Qsys Address Mapping Query
I have a Qsys design in which NIOS II data master is connected to Avalon slave of peripheral (Stepper driver). Here the width of the address bus of the peripheral is 3-bits. So, when I assign base address for the peripheral, I was expecting the tool to assign the end address automatically by looking at the address bus width of the peripheral. Hence, if I assign base address as 0x0000 0000, i was expecting to see the end address as 0x0000 0007 (because the address bus is 3-bits). But the tool assigned the end address as 0x0000 001F. When I checked the HDL of Qsys design, I understand additional 2-bits has been appended to the address bus. I am totally confused on this. I know I am missing out something. Can anybody enlighten me on this?
3 Replies
- Altera_Forum
Honored Contributor
At your peripheral hw.tcl, check the addressUnits of your Avalon Slave. Make sure that it is SYMBOLS.
- Altera_Forum
Honored Contributor
I just now checked the hw.tcl of the peripheral. I do not see "SYMBOLS" in the file. I have pasted below the code in hw.tcl :
add_interface_port s1 s_cs chipselect Input 1 add_interface_port s1 s_address address Input 3 add_interface_port s1 s_read read Input 1 add_interface_port s1 s_readdata readdata Output 32 add_interface_port s1 s_write write Input 1 add_interface_port s1 s_writedata writedata Input 32 - Altera_Forum
Honored Contributor
You are missing a bunch of interface property assignment, example below:
add_interface s1 avalon end set_interface_property s1 addressunits symbols set_interface_property s1 associatedClock clock set_interface_property s1 associatedReset reset set_interface_property s1 bitsPerSymbol 8 set_interface_property s1 burstOnBurstBoundariesOnly false set_interface_property s1 burstcountUnits WORDS set_interface_property s1 holdTime 0 set_interface_property s1 linewrapBursts false set_interface_property s1 maximumPendingReadTransactions 0 set_interface_property s1 maximumPendingWriteTransactions 0 set_interface_property s1 readLatency 0 set_interface_property s1 readWaitTime 1 set_interface_property s1 setupTime 0 set_interface_property s1 timingUnits Cycles set_interface_property s1 writeWaitTime 0 set_interface_property s1 ENABLED true If you are missing the above assignment, the slave is treated as WORD by default. Do add the above code into your hw.tcl. Modify the properties as necessarily, read latency and etc.