Forum Discussion
New ContributorPurchase of New Intel FPGA Development Board
Thanks for the Kudos. I do understand . . . I have had the same issues.
From a high level / top level viewpoint, you will be able to update the RELEASE version of the download if need.
Overall here are the details:
Basically, there is no First Stage Boot Loader with Nios (compared to something like Zynq 7000 series for example.) The Cyclone 10 LP does not have an ARM A53 or A9 in it . . . so you will have to use Nios and Nios can boot directly from internal memory if the program fits within your internal RAM. For most Nios programs, say 64K to 128Kbytes of memory is sufficient ... and the Cyclone 10 LP should have enough internal RAM (and I believe it also has HyperRam attached to it that you can access) that you should be okay.
Basically, you can program the flash memory through the USB blaster, and when the FPGA boots the Nios program will be in the flash. You just have to convert the ELF file in Eclipse using mem_init_generate for make targets in Eclipse to convert the ELF to hex, and then attach the hex to your Quartus project and compile ... and the Nios instructions will be in the external flash memory. So in summary:
1. Develop your C in Eclipse, JTAG downloading your design and testing
2. When finished, convert ELF to hex with mem_init_generate in Eclipse
3. Attach hex to Quartus project
4. Compile Quartus project
5. Program flash memory with Quartus programmer
When you power cycle, you should see your Nios software executing (such as through Uart, led, etc.)
Regards, James
New ContributorHi, James!
Thank you for your informative reply.
Since I am primarily a Xilinx programmer and Xilinx gives away its IDE free of charge (Vivado + Vitis) when you wrote:
" the Max10 System Manager contains code for the USB blaster JTAG programmer and that is not free either, that is why it is programmed into the chip but the source code is not available ... "
I failed to completely understand the true meaning of your reply in terms of "design limitations".
Whenever I bought a FPGA development board, whether it be Lattice or Xilinx, I could always download the examples the company supplied to its customers. Please take notice of this part of the question that I had originally posed:
" When I looked at the software examples I noticed that they make reference to Quartus Prime Standard, not 'Quartus Prime Lite' ..."
Can I successfully download the example software using the Quartus Prime Lite and will my programs run as expected?
Can you also tell me what the "design limitations" will be if I do not have the source code for the MAX 10 System Manager ( a "hands on" example of a design limitation would be helpful for me to understand what the design limitation really is)?
Thank you for your initial reply. I gave you a Kudo!
James_BContributor
Thanks for the Kudo. I do understand the challenges when adjusting between Microblaze and Nios.
With regards to questions:
1. The Max10 is acting like a USB blaster, and the code for that is proprietary. The Max10 is flash based, and boots from it's own internal flash memory. So when you power up the board, the functionality of the Max10 acting as like a USB blaster that allows you to program the other FPGA on board (in this case Cyclone 10) with just connecting a USB cable to the board and using the Quartus programmer. The Max10 handles the JTAG translations, etc. as it is like an onboard USB blaster.
2. You are able to download any example code for the board using Quartus Lite for Cyclone 10 LP. You just need to connect a USB cable to the board and have Quartus programmer open. The JTAG signals will go through the on board USB blaster in the Max10 as described in (1) above. I would suggest a basic heartbeat program blinking a LED first before anything to reduce compile time and have a very simple working example, to validate that Quartus is all setup properly.
Regards, James
- TechDeveloper
Dear James;
Thank you for your reply. You got another KUDO!
I definitely understood your answer for question 1 and got the "gist" of the answer for question 2.
However, the quote below is the context to which question 2 is based:
"...Intel MAX 10 FPGA, pre-programmed System Manager ASSP functions (Not programmable by the user)"
Can anyone tell me what "...(Not programmable by the user)" means in terms of software development limits?
Does this mean that I cannot modify the first stage bootloader or modify the "control" handoff? In other words, if there is a problem with the RELEASE version of the download, I can't remedy my problem?
- James_B
Thanks for the Kudos. I do understand . . . I have had the same issues.
From a high level / top level viewpoint, you will be able to update the RELEASE version of the download if need.
Overall here are the details:
Basically, there is no First Stage Boot Loader with Nios (compared to something like Zynq 7000 series for example.) The Cyclone 10 LP does not have an ARM A53 or A9 in it . . . so you will have to use Nios and Nios can boot directly from internal memory if the program fits within your internal RAM. For most Nios programs, say 64K to 128Kbytes of memory is sufficient ... and the Cyclone 10 LP should have enough internal RAM (and I believe it also has HyperRam attached to it that you can access) that you should be okay.
Basically, you can program the flash memory through the USB blaster, and when the FPGA boots the Nios program will be in the flash. You just have to convert the ELF file in Eclipse using mem_init_generate for make targets in Eclipse to convert the ELF to hex, and then attach the hex to your Quartus project and compile ... and the Nios instructions will be in the external flash memory. So in summary:
1. Develop your C in Eclipse, JTAG downloading your design and testing
2. When finished, convert ELF to hex with mem_init_generate in Eclipse
3. Attach hex to Quartus project
4. Compile Quartus project
5. Program flash memory with Quartus programmer
When you power cycle, you should see your Nios software executing (such as through Uart, led, etc.)
Regards, James
