Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Pseudo code for finding optimum pll values

Hi,

running late in a project I have one quick question:

Does anyone have any pseudo code or c code for finding the PLL params for dynamic reconfiguration?

The downcounters are straight enough, but i have not found enough info for designing a program that also considers the VCO settings, Loop filter and so on.

Especially when using multiple clocks. I wrote this for a cypress pll a couple of years ago, but of course it uses a different scheme.

We happed mapped the Pll_reconfig to some registers in nios, and that works great.

Info anyone? I'll try alteraforum too.

Regards,

Apus

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    <div class='quotetop'>QUOTE (agdepus @ Aug 20 2009, 02:22 PM) <{post_snapback}> (index.php?act=findpost&pid=23537)</div>

    --- Quote Start ---

    Does anyone have any pseudo code or c code for finding the PLL params for dynamic reconfiguration?[/b]

    --- Quote End ---

    Try looking in the Quartus simulation library for the altpll;

    quartus/eda/sim_lib/altera_mf.vhd

    There&#39;s a bunch of calculations in there that check for valid settings,

    so you can probably use those for your design.

    Alternatively, you can use the MegaWizard to setup the parameters

    and then generate a .mif file. That file will contain the valid bit

    settings. AN367 has the valid settings for the Stratix II device PLLs.

    Cheers,

    Dave

    (who just happens to be playing with the altpll scan chain today)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Great,

    didn&#39;t think of that one. Now where is my vhdl to c converter.......:-)

    I&#39;ll post the results if anyone is interested.

    Apus