Programming non-EPCS serial flashes?

Hi Mike,

We use the ST Micro serial flash because its a drop in replacement for the Altera. (M25P64 for the 64mbit)

The point for your problem is that the ST Micro parts are well documented and you may be able to create an emulator layer.

Ken

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originally posted by kenland@Oct 15 2006, 04:29 PM

hi mike,

we use the st micro serial flash because its a drop in replacement for the altera. (m25p64 for the 64mbit)

the point for your problem is that the st micro parts are well documented and you may be able to create an emulator layer.

ken

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18708)

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Yes, Altera EPCS parts seems to be no more that "Rebranded" M25P ST parts. You can convince yourself by comparing EPCS datasheet and M25P datasheet (command set).

The only different thing is device code (but it seems logical, no ? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif )

Another thing : I don&#39;t know if quartus programmer check this ID code before programming. So I fear that Quartus programmer will reject non Altera devices. But I&#39;m not sure . Anybody knows ?

BR.

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originally posted by bigboss25+oct 16 2006, 03:07 am--><div class='quotetop'>quote (bigboss25 @ oct 16 2006, 03:07 am)</div>

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<!--quotebegin-kenland@Oct 15 2006, 04:29 PM

hi mike,

we use the st micro serial flash because its a drop in replacement for the altera. (m25p64 for the 64mbit)

the point for your problem is that the st micro parts are well documented and you may be able to create an emulator layer.

ken

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18708)

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Yes, Altera EPCS parts seems to be no more that "Rebranded" M25P ST parts. You can convince yourself by comparing EPCS datasheet and M25P datasheet (command set).

The only different thing is device code (but it seems logical, no ? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif )

Another thing : I don&#39;t know if quartus programmer check this ID code before programming. So I fear that Quartus programmer will reject non Altera devices. But I&#39;m not sure . Anybody knows ?

BR.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18709)</div>

[/b]

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In addition, you might want to read this :

http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf (http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf)

BR.

Hey,

You can also use Spansion parts as drop-in replacements for EPCS devices. They are ready to plug&#39;n&#39;play and are recognised as &#39;EPCS&#39; devices by QuartusII.

Cheers,

Claire

Thanks for the responses, but I&#39;m not looking for a drop-in replacement for an EPCS; that configuration would still only allow a single firmware image.

Has anyone heard anything from Altera about the Nios Flash Programmer supporting arbitrary flashes by allowing you to build your own firmware? Failing that, does anyone have the source to the Nios Flash Programmer firmware ROM?

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originally posted by mike desimone@Oct 20 2006, 10:17 AM

thanks for the responses, but i&#39;m not looking for a drop-in replacement for an epcs; that configuration would still only allow a single firmware image.

has anyone heard anything from altera about the nios flash programmer supporting arbitrary flashes by allowing you to build your own firmware? failing that, does anyone have the source to the nios flash programmer firmware rom?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18818)

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Just a suggestion, considering the following:

Keep your AVR and an EPCS in which your store consecutively your 3 bitstreams.

Maybe it is possible to do the following:

- wire SPI programmation bus to your AVR and your EPCS, (in parallel)

- let the flash programmer access to the EPCS through SPI, as normally. During this programming phase AVR must be "tris-stated" on SPI lines.

- during boot, let the AVR override the SPI bus to initiate an SPI READ command to the EPCS , at the **desired ** offset location. This will set the current pointer in the EPCS.

- then remove AVR from SPI bus, and let the FPGA boot from this starting address. If you&#39;re lucking, (to be checked) , the FPGA will no rewrite the starting pointer (0 value) , just reading data from the current value. But I&#39;m not sure about that. You should have a look to EPCS boot sequence (active serial mode).

Once again, this has to be checked.

BR

That&#39;s kind of what we&#39;ve been trying to do all along, running the Altera in Passive Serial mode and having the Atmel initiate the read command before enabling the configuration on the Altera and then just sitting back and generating a clock while the bitstream loads.

What you&#39;re suggesting, at its face, won&#39;t work since the Continuous Read commands require an address to be specified in the command, so the Altera will override it. However, a slightly changed procedure might work:

1) Hold nCONFIG low.

2) Activate the AVR&#39;s SPI port.

3) Pull nCSO low.

4) Send the start of the Continuous Read command (0x03, AH, AM, AL).

5) Deactivate the SPI port.

6) Release nCONFIG, but keep nCSO low.

7) Altera does its thing in AS mode, which hopefully only does its own Continuous Read command, which just wastes the first four bytes in the flash (which should be programmed to 0xFF anyway).

8) When the Altera is done, release nCSO, turning over the ASMI port to the Altera. Flash programming can be achieved through the usual Nios Flash Prorammer means.

The Altera would therefore be wired for Active Serial (MSEL[1:0] = 00). Since nCSO and ASDO are driven as outputs in that mode, they would need to go through series 4.7K or so resistors so that the Atmel can overdrive them when it needs to.

This is an interesting possibility. I&#39;m going to be hooking up the EPCS1 on one of my boards to see what it does.

Okay, here&#39;s what I see on the EPCS1 when I reconfigure my Cyclone EP1C3:

nCS falls

Send 0x05, receive 0xFF: Read status register command

Send 0xFF, receive 0x00: SR is 0.

nCS rises, then falls after 450 ns.

Send 0xAB, receive 0xFF: Release from Power Down and read signature

Send 0x00, receive 0xFF: dummy byte# 1

Send 0x00, receive 0xFF: dummy byte# 2

Send 0x00, receive 0xFF: dummy byte# 3

Send 0x00, receive 0x10: Signature is 0x10 (EPCS1) (I saw 9 bits clocks, not 8, for this byte)

nCS rises, then falls after 2.2 us.

Send 0x03, receive 0xFF: Read array continuous

Send 0x00, receive 0xFF: address byte# 1

Send 0x00, receive 0xFF: address byte# 2

Send 0x00, receive 0xFF: address byte# 3

After this, it kept nCS low while reading the data bytes.

So much for hijacking AS mode. I can still do what I was planning on in the first place, but maybe I&#39;ll need to have the AVR control the MSEL0 pin so I can switch it between AS mode and PS mode, using PS mode during configuration and AS mode during runtime (so the ASDO and nCSO pins on the Altera work for the flash programmer).

I&#39;m amused it checks the signature byte.

hi,

May I know is anyone ever try to use Micron N25Q for Arria V device under AS configuration and program the FPGA with this chip correctly successfully?

Rgds,

tong