problems with flash and tri-state-bus

Hi everybody,

on a custom board, I use a tri-state-bus and cfi flash component to connect an amd compatible flash device with a 16 bit wide bus.

The entrypoint to my application is alt_main, no HAL drivers or interrupts are initialized. I am just using macros from io.h to access the flash.

# define AUTO_SELECT() {

(IOWR_16DIRECT((flash_base), 0xAAA, (ushort)0xAA));

(IOWR_16DIRECT((flash_base), 0x555, (ushort)0x55));

(IOWR_16DIRECT((flash_base), 0xAAA, (ushort)0x90)); }

# define CFI_QUERY() (IOWR_16DIRECT((flash_base), 0xAA, (ushort)0x98))

# define READ_RESET() (IOWR_16DIRECT((flash_base), 0xAAA, (ushort)0xF0))

# define READ_DIRECT(src, offset) (IORD_16DIRECT(src, (ushort)offset))

int main (void) __attribute__ ((weak, alias ("alt_main")));

int alt_main(void)

{

unsigned char *flash_base;

int val[10];

flash_base = (unsigned char *) EXT_FLASH_BASE;

while(1)

{

usleep(5000000);

CFI_QUERY();

val[0] = READ_DIRECT(flash_base, 0x20);

val[1] = READ_DIRECT(flash_base, 0x22);

val[2] = READ_DIRECT(flash_base, 0x24);

READ_RESET();

AUTO_SELECT();

val[3] = READ_DIRECT(flash_base, 0x00);

val[4] = READ_DIRECT(flash_base, 0x01);

READ_RESET();

}

}

The application just reads a few values from the CFI table and the manufacture and device ids.

I am using signal tap to monitor the adress, data, read, write and select pins.

Well, signal tap shows mor accesses to flash than the system should perform!

After CFI_QUERY() I can see 6 read cycles wehre only 3 should take place. The first to read cycles are doubled and and the last one reads from offset 0x26 (my last read incremented by 2).

In AUTO_SELECT() there is an additional write cycle to the address of my last cycle incremented by 2.

Does anybody know where the additional read and write cycles come from???

--wolfgang