problems with flash and tri-state-bus

Ok, the problems seems to be related to the avalon bus.

As I understand, the additional read cycles are related to the dynamic addressing

and are ok, because the additional data is discarded by the bus.

The additional write cycle indeed is a problem. As far as I could figure out, it occurs only writing to an odd address.

I do not know if this is mentioned in any documentation, at least I could not find it. But it is known for sure, that I know after having a closer look to the HAL cfi flash driver and the development board schematics.

Have fun,

--Wolfgang