Forum Discussion
Honored ContributorProblems with Cyclone IV and DP83848C
Dear all, I've made my own board of Cyclone IV EP4CGX110CF23C7. And i want to make a ethernet module with DP83848C which is surpported by the TSE core.
However, when i have completed my SOPC system and downloaded the nios program, it seems that something wrong happened to my program and i am confused by this problem for several days. When i run my project as NIOSII hardware on NIOS SBT v12.1, the nios ii console displays as following: interniche portable tcp/ip, v3.1copyright 1996-2008 by interniche technologies. all rights reserved.
prep_tse_mac 0
your ethernet mac address is 00:16:36:fc:14:2d
static ip address is 192.168.1.234
prepped 1 interface, initializing...
netinit: calloc failed getting buffer 17
inet startup error: unable to initialize net
panic: ip
dtrap - needs breakpoint
ip_exit: calling func 0x9e7a4 Here are some attachments of my program. PS: 1. I turned off the DHCP and set the board IP address 192.168.1.234. 2. I created the program from the template Simple Socket Server. 3. There is no NAND flash on my board and i set my board MAC address 00:16:36:fc:14:2d
27 Replies
Altera_Forum--- Quote Start --- Okay. Your board isn't even answering the first ARP request, so you need to use signaltap to figure out if the ARP request gets on the PHY's rx interface, and if your system answers on the PHY's tx interface. --- Quote End --- The last attachment is somewhere wrong.Here is the correct one.- Altera_Forum--- Quote Start --- Uhm..But can you introduce it more detailedly ? I'm a beginner in the field of network and i cannot recognize how the ARP request transmitted to the board. Or may i have your email or msn/QQ in order to contact you conveniently. The following is the signaltap screen shot when ping the board. --- Quote End --- it is not related to the FPGA. I just asked what is your network topology. A) computer <====ethernet cable===> FPGA board B) computer <====ethernet cable===> network switch <====ethernet cable====> FPGA board which one you used?
- Altera_Forum--- Quote Start --- I've tried to use a 10/100Mb switch but there is still no connect between the board and the host pc --- Quote End --- OK got you. could you upload your network related connection from you FPGA top-level code?
- Altera_Forum--- Quote Start --- OK got you. could you upload your network related connection from you FPGA top-level code? --- Quote End --- Here is my project file.
- Altera_Forum
In your signaltap project, you need to add the enet_rx_en signal (or maybe it's called enet_rx_dv). Then set a trigger to a rising edge or that new signal and see if it picks up anything. You can also regroup enet_rx[0] to enet_rx[3] so that you will directly see the hex digit.
- Altera_Forum
Please do you have any results in your troubleshooting the DP83848C PHY connection? I am having the exact same problem and I can see the data packets on RX[3..0] lines, also the RXDV signal is OK. What I can not see is any response on the TX[3..0] lines or TXEN. TXCLK, RXCLK are fine also. The link status is also OK, I have the very same console output as you on the top of this thread.
Have you solved your issue? Do you have any recommendations what to try,.. or? Thank you very much for the reply... Jan. - Altera_Forum
What do you get on the other side of the TSE core? Does it detect the received packet and put it on its avalon stream rx interface?
- Altera_Forum
I have solved the issue by using another nios core(nios.sopc file) from my classmate. But i still don't know what causes it.
- Altera_Forum--- Quote Start --- What do you get on the other side of the TSE core? Does it detect the received packet and put it on its avalon stream rx interface? --- Quote End --- Thanks for the reply. Could you please describe how to check the avalon stream interface?... I have classic TSE connection with the SGDMA_RX and the receive port of the TSE is going to SGDMA.RXIN port. Thanks for the reply...
- Altera_Forum--- Quote Start --- What do you get on the other side of the TSE core? Does it detect the received packet and put it on its avalon stream rx interface? --- Quote End --- I have tried to use signal tap to catch the physical pins and the ff_rx_data of the TSE.. I am not sure if this is correct.. But I can see that ff_rx_data is not changing. Please find the attached file: https://www.alteraforum.com/forum/attachment.php?attachmentid=7792
