Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Problems Uploading to JTAG Device #2

Is there some configuration step I'm missing that will make the "Upload" feature work properly when the FPGA is Device# 2 on the JTAG chain? Background: I'm working with an Altera ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Thanks Doug,

I'll couple that with some similar information from the DSP board thread that appears to address custom board memory maps using command line options in the SDK shell.

I needed a good excuse to get outside of the IDE and get more familiar with the SDK shell anyway... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif