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Altera_Forum
Honored Contributor
16 years agoOk, I got this working, thanks hippo.
In case it helps someone: It turns out that although Altera documentation says the CPU reset offset is 0x100000, the offset they actually use in the standard example (version 7.20) is 0x0. This can be found in the PTF (other useful lines included):reset_offset = "0x00000000";
break_offset = "0x00000020";
exc_offset = "0x00000020";
CPU_RESET_ADDRESS = "0x4000000"; or in the generated linux2.6.x/include/asm/nios2.h: #define CPU_RESET_ADDRESS 0x04000000# define CPU_EXCEPT_ADDRESS 0x00000020 So, the command to generate the flash image is: elf2flash --base=0x04000000 --end=0x04FFFFFF --reset=0x04000000 --input=zImage --output=zImagebf.flash --boot=/opt/altera/nios2eds/components/altera_nios2/boot_loader_cfi.srec However, the FPGA is stored at offset 0x2000 (so, addess 0x04002000), so I don't know how this actually is supposed to ever work. Configuring the FPGA using nios2-configure-sof works though, then download Linux into flash, then the CPU reset button on the bottom of the NEEK comes in useful. With a sof/ptf changed in sopc to a CPU reset offset of 0x500000 (--reset=0x04500000) (anything large enough to fit the FPGA (sof) flash image below it should work), I can program both the FPGA and the Linux image into flash and boot into Linux from a cold start. So, all solved except for# 3 (running uclinux without JTAG console). Don't really need that since "Bypass output when no connection" works nicely, but should it work at all?