New ContributorProblem writing the NIOS II program to the EPCS controller.
I have a problem writing the NIOS II configuration and program to the EPCS controller.
I've read the entire Internet on this topic and 70 posts on this forum. I've tried everything that's written here.
My configuration. Chinese board OMDAZZ Cyclone 4E CPLD EP4CE6E22C8.
I wrote a simple program that works in OnchipRAM. It blinks the LED and displays information on the LED indicator. This program was store to the OnchipRAM image and converted to a JIC file. It works.
The EPCS controller is connected to the data bus, instruction bus, reset (including from JTAG) and PLL output 12 MHz. The EPCS base address is 0x8002000. NIOS II reset is assigned to the same address 0x8002000. Exception Vector is in OnchipRAM. The linker is configured to generate code in OnChip.
allow_code_at_reset and the other 4 keys are disabled. log_port is disabled. In the linker settings I also see the correct reset address on the EPCS base.
I am using Quartus II 13.1. I saw that there is a problem for Quartus II 13.0:
Boot from Quad Serial Configuration(EPCQ) and Serial Configuration (EPCS)
https://www.intel.com/content/dam/support/us/en/programmable/kdb/rd11122013-865/nios-ii-boot-from-epcq-and-epcs-in-quartus-ii-13-0.pdf
Is this problem still present in Quartus II 13.1? Is there a patch for this?
I read that EPCS boot only works with NIOS II/f processors. Is this true?
I tried the steps described here:
When generating nios_load1.sopcinfo I get two warnings:
Warning: nios_load1.epcs_flash_controller_0: epcs_flash_controller_0.external must be exported, or connected to a matching conduit.
Warning: nios_load1.epcs_flash_controller_0: Interrupt sender epcs_flash_controller_0.irq is not connected to an interrupt receiver
I think it's not critical.
I know several ways to get a HEX file. This is the only way to get a working file. I took this method from mem_init.mk.
elf2hex NIOS_LED_SDRAM_APP.elf 0x08008000 0x0800cfff --width=32 --little-endian-mem --create-lanes=0 ../../output/EPCS_w.hex --verbose
I inserted this file as an OnchipRAM image to check. It works. For write to EPCS, I converted the EPCS_w.hex file to the HEX byte format as described on the forum:
Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to OFF
Load the EPCS_w.hex file to Kvartus
Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to On
Save the EPCS_w.hex file.
Then I loaded the file EPCS_w.hex into the converter to get the JIC file (also load SOF file). The converter created a JIC file with a report in SDRAM_LED.map
Page_0 0x00000000 0x00023038
EPCS_sw.hex 0x00023039 0x00025DA0
Tried different offsets as recommended on the forum. Turned off and on SOF file compression. Doesn't help.
Another way to get a HEX file
sof2flash --input=../../output/NIOS_II_My.sof --output=hw.flash --epcs
nios2-elf-objcopy --input-target srec --output-target ihex hw.flash ../../output/EPCS_hw.hex --verbose
elf2flash --input=NIOS_LED_SDRAM_APP.elf --output=sw.flash --epcs -after hw.flash --verbose
nios2-elf-objcopy --input-target srec --output-target ihex sw.flash ../../output/EPCS_sw.hex --verbose
creates a HEX file that does not work even as an image in OnchipRAM. Can you tell me why? What did I do wrong here?
I'm confused with the nios_load1_epcs_flash_controller_0_boot_rom.hex file. It is created when generating nios_load1.sopcinfo in the sopc\nios_load1\synthesis\submodules folder. But when
using the mem_init_generate script in the mem_init/hdl_sim folder, this script also creates the same file. But if disable allow_code_at_reset in the linker and 4 keys below, this file consists of only one line - the end of the file.
As far as I understand, the nios_load1_epcs_flash_controller_0_boot_rom.hex file is an image of the ROM disk of the EPCS controller. Could it be that when generating nios_load1.sopcinfo, the wrong file is created or should I create this file myself to replace the generated one?
When programming Flash Programmer gives an error
Info: No EPCS registers found: tried looking at addresses
Info: 0x08002000, 0x08002100, 0x08002200, 0x08002300 and 0x08002400
Error: Error code: 8 for command: nios2-flash-programmer
"E:/Q_Project_03_03/NIOS_LED_SDRAM/Software/NIOS_LED_SDRAM/flash/NIOS_II_My_epcs_flash_controller_0.flash" --base=0x8002000 --epcs --sidp=0x80010A0 --id=0x12345678 --timestamp=1741934460 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose
However, if program the JIC file, the recording and checking are successful, the hardware works, but NIOS II does not start.
I ask for help back up this situation me led to a dead end and not to see a solution. I"m have experience electronics and programming. I will understand even two words where I was wrong.
Sorry for my bad English
Hi @Megavolt91,
Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
Thanks for the details explanation, appreciate the effort on explaining the situation, it definitely helps us to understand the situation and others too.
Just to clarify, you are able to program to Nios II configuration to EPCS controller now and Nios II is also starting up. However there is confusion in the addresses?
Note: Nios II has been deprecated and no longer supported, hence perhaps it is advised to moved to Nios V, however we would try our best to clarify on your situation.
Best Wishes
BB
