Forum Discussion
Problem writing the NIOS II program to the EPCS controller.
- 1 year ago
Hi @Megavolt91,
Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
Thanks for the details explanation, appreciate the effort on explaining the situation, it definitely helps us to understand the situation and others too.
Just to clarify, you are able to program to Nios II configuration to EPCS controller now and Nios II is also starting up. However there is confusion in the addresses?
Note: Nios II has been deprecated and no longer supported, hence perhaps it is advised to moved to Nios V, however we would try our best to clarify on your situation.
Best Wishes
BB
But i have problem sw.flash is not proggramed:
22.03.2025 9:53:31 - (FINE) sof2flash: Starting
22.03.2025 9:53:38 - (FINE) sof2flash: Done
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x00000000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Valid registers found
EPCS signature is 0x14
EPCS identifier is 0xEF4015
Using EPCS size information from section [EPCS-EF4015]
Device size is 2MByte (16Mbit)
Erase regions are:
offset 0: 32 x 64K
EPCS status is 0x00
: Checksumming existing contents
00000000 : Verifying existing contents
00000000 : Already programmed with correct data
00010000 : Verifying existing contents
00010000 : Already programmed with correct data
00020000 : Verifying existing contents
00020000 : Already programmed with correct data
Checksummed/read 147kB in 14.5s
Erase not required
00000000 ( 0%): Programming
00010000 ( 0%): Programming
00020000 ( 0%): Programming
Programmed 147KB in 0.0s
No change to device contents
Leaving target processor paused
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x00000000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Write to EPCS registers failed
Not here: can't write 0x1 to SPI_SLAVE_SEL
Write to EPCS registers failed
Write to EPCS registers failed
No EPCS registers found: tried looking at addresses
0x00000000, 0x00000100, 0x00000200, 0x00000300 and 0x00000400
Leaving target processor paused