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Altera_Forum
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13 years ago

Problem with the Nios II 11.1sp2 Software Build Tools

Hello,

I'm working with the Nios II for few weeks with this hardware and software:

Terasic DE0 Nano

Windows 7 64 Bit

Altera Quartus 11.1 SP2

Nios II 11.1sp2 Software Build Tools for Eclipse

I can easily create a Nios design with SOPC Builder or QSys, download it to the FPGA and create a BSP and application. The application runs on the target without problems.

But when I close the toolchain and restart it the next day, I always get this error when I'm trying to launch the application (build is without errors):

"The system console model is invalid. Cannot launch"

Does anyone have an idea what this message means?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Go to the Run/Run Configurations

    On The "Nios II Hardware" Delete the sub itens.

    Create a "NEW NIOS II HARDWARE SETUP".

    The problem was because the files from previous eclipse software are incompatible to the new eclipse
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I’m glad someone replied to this post, but there’s more going on here. I’ve had this issue (the “The system console model is invalid. Cannot launch.”) off and on since I switched to Q11. I’ve found a few things that seem to toggle the problem, but I’m currently stuck and none of my little tricks are able to get past this. Things that have worked in the past: a) Close/reopen Eclipse IDE. b) Delete/rebuild project (importing source files to new system). c) I have a clock in my qSys system that doesn’t come alive (by design) on startup. I found that I can’t attach the debugger before this clock comes up even though NIOS is running on a different clock.

    But now I’ve worked my way into a corner it seems, and none of these fix the problem. The error message has no details in it pointing me to something I can go look at. I’m just trying blindly to find things that clear this issue. If anyone has any ideas, more input would be appreciated.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'll see if have other options to modify.

    In principle the problem appears to be in some configuration files.

    If you want to post the files, I will take a look.

    Or a simplifyed system with the same error.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I found that doing a hardware reset on my board clears the issue. I'm still not sure what’s causing it or what the error message actually means, but for now it seems I have a way out.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I believe this has to do with the JTAG connection. Try going into run/run configuration and selecting the target connection tab. Click on refresh connection, then deal with any issues that may be exposed there. Sometimes just refreshing the connection is enough to clear the error message.

    This will also occur if the Timestamp and/or System ID do not match.

    Good luck...
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    When I got this problem I checked the ignore mismatched system ID and timestamp, under the target connection tab.

    I hope this helps,

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I like having the system ID enabled since it gives me a quick indication when things go bad… and if it’s gone bad I don’t want to spend time looking any further.

    I haven’t entirely solved this issue yet, but it’s not nearly as frequent since I fixed an electrical contention issue on my board. I was driving a signal off chip that goes to a multi-purpose pin on an external device. This multi-purpose pin starts out as a chip enable so the FPGA starts out driving the signal, and then my code would reconfigure the device to make the pin an output. The timing of this sequence is important since I have to drive the FPGA pin while it’s a chip enable, then disable my driver as the external chip switches the pin to an output function. I believe my timing was off and I continued to drive the FPGA pin while the external chip was also driving the multi-purpose pin on its end. Once I straightened this out, the “The system console model is invalid. Cannot launch” problem seems to have abated.

    When it does come up, refreshing the jtag connection works most times.

    Thanks for the feedback