Honored Contributor
Honored ContributorAll,
Do any of you have an archived copy of your pre-quartus-4.2 design somewhere? If so, can you carefully examine the top-level SOPC-Builder-generated module and look at the address bus(es) going to your external peripherals please (in comparison to the one that was just generated and doesn't function)? The reason I ask: there was a change in Quartus II 4.2 (SOPC Builder) -- a bug fix in how address busses are generated -- that may *remove* a top-order address pin in interfaces to certain external busses. So for example, you may have previously had A[6..0] popping out the top and now have A[5..0]. As you can imagine this can be a problem if software was written to use this address pin, or depending on how the A[] bus is hooked up to the outside world in your top-level HDL or schematic capture. We are working on posting a detailed explanation of this problem and workarounds to the Altera website at the moment -- this *may* not even be the problem you're seeing in your system, but it sounds awfully familiar. I'd type out a long-winded explanation this second but I am hoping to have a web-link that I can paste here shortly. EDIT: what I say above applies for the symptoms niosIIuser is reporting. What MiR was seeing was something different, based on the new 'Component Builder' - that is a separate discussion but one that should not require going back to Nios II 1.01 to solve.
