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Honored Contributor
Honored Contributorproblem with mutex core
Dear all, I've created a qsys system composed of two NIOS, each one attached to its on-chip memory that contains its program. the two processors are connected to a shared RAM protected via a ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Are you sure that both CPU are connected to the same shared memory, that SHM is the correct address, and that this memory isn't used for anything else? (including the text, ro, rw, bss, stack and head sections) I'd suggest to put SignalTap probes on the shared memory control signals to verify that the first CPU is correctly writing the value and see what the second one is reading. --- Quote End --- Yes I'm sure that both CPU are connected to the shared RAM, this memory is only connected to cpu data masters, to clk and reset signals Could you please tell how use and put SignalTap probes on the shared mem? what are signal tap probes? is there any tutorial??
