Problem with IORD and IOWR instructions

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Hi BadOmen,

where enable the optimizations? I'm using the default setting of NIOS II SBT tool to compile both codes

I want in a first step be sure of the functioning of IORD and IOWR and then use the mutex to access the shared memory

any help will be appreciated,

Thanks

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I typically work from the command line so I forget where it is but a debug profile would normally contain -O0 optimization (i.e. no optimization). For that updated code that polls for 9 to be read back from memory try making the 'j' variable volatile, regardless of whether optimizations are enabled or not that should prevent the loop from being removed.

Also are you sure your both processors are actually running code? Each CPU should have it's own BSP (can't have them both sharing read/write, heap, and stack regions) so you should be able to run them independent of eachother to make sure they execute code properly up to a certain point. Once that's verified then you can download the code as a multi-download group (whatever it's called in the IDE). I normally find it easier to coordinate multiple processor downloads from the command line like this:

nios2-download -i 0 -g <elf1.elf>

nios2-download -i 1 -g -r <elf2.elf>

nios2-terminal -i 0

nios2-terminal -i 1

The -i lets you pick which Nios II JTAG debug module/JTAG UART you are using. The -g tells nios2-download to start executing code and -r means reset the target. Normally I open one terminal window per command shell so that I can watch the output of all the processors at the same time.

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I typically work from the command line so I forget where it is but a debug profile would normally contain -O0 optimization (i.e. no optimization). For that updated code that polls for 9 to be read back from memory try making the 'j' variable volatile, regardless of whether optimizations are enabled or not that should prevent the loop from being removed.

Also are you sure your both processors are actually running code? Each CPU should have it's own BSP (can't have them both sharing read/write, heap, and stack regions) so you should be able to run them independent of eachother to make sure they execute code properly up to a certain point. Once that's verified then you can download the code as a multi-download group (whatever it's called in the IDE). I normally find it easier to coordinate multiple processor downloads from the command line like this:

nios2-download -i 0 -g <elf1.elf>

nios2-download -i 1 -g -r <elf2.elf>

nios2-terminal -i 0

nios2-terminal -i 1

The -i lets you pick which Nios II JTAG debug module/JTAG UART you are using. The -g tells nios2-download to start executing code and -r means reset the target. Normally I open one terminal window per command shell so that I can watch the output of all the processors at the same time.

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Yes I'm using same things: command lines

I put j as volatile but I've always same problem, Nios2 read a false value from the shared memory

Hi,

is there any problem if each CPU has its own on-chip memory containing the code to execute

or I should have one instruction memory shared between the two NIOS???

But I've always same problem,

please tell me how to share a memory between two cpu in order to share data???

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Depending on what I'm doing I typically either use a shared memory and a mutex or FIFOs to share data back and forth. You just connect them to the data master of each processor and both should be able to issue reads/writes to the shared data.

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Pl

what version of qsys and NIOSII SBT are you using??